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The
SHIVA
Reconfigurable Processor core macrocell
SHIVA
Processor Core application targets:
 Fast
data stream processing in communications.
Fast
optimized parallel control of real time systems.
Fast
real time, parallel independent multichannel Digital Signal Processing.
Real
time compression and decompression.
Real
time security encryption and decryption.
Heterogeneous
CPU SoC unification and features extension with migration to
SHIVA core.
Real
time high throughput heavy Audio and Video (MPEGx, HDTV, Xvid,
DivX, etc.) data streaming manipulation.
The SHIVA processor core has difference in
creating and using the blocks and cells for tailoring in a design.
This has significant implication on the speed, how the data will be
processed, and the way it occurs.
The architecture of the core and it's internal
cells, allows the best data manipulation and interconnection possible.
The I/O throughput of the data is not a limitation anymore.
This allows, the performance of an ASIC and
programmability of the microprocessors, to come together.
The SHIVA processor core, takes the design
performance and efficiency, very close to an ASIC implementation.
The computational parallelism creates performance,
near the theoretical calculations.
Reconfigurability is pushed to the highest
degree, and is the main focus in the core and its options.
Thinking in hardware allows you to start with
the high level programming code and silicon-area/clock-frequency trade
off, and end with your design done.
Options
The
core comes with an software suite and retargetable ILP compiler, which
can be used for a standard, custom processor code generation, or,
for the SHIVA core.
A
high level compiler, takes C/C++ or Ada code, and produces Microsoft
Intermediate Language (MSIL)
format files. /compilers from Borland
and Microsoft/
An alternative is the GNU
tools. (support for MatLab
m-files code compilation is planned in the future)
The
low level ILP compiler, takes couple of instruction set formats, /including
MSIL format/, and produces byte code for the program memory.
The
reconfigurability of the core and the ILP compiler, allow extension
of a basic processor configuration with custom processor instructions,
or, replacement of an already existing core in a design, with different
and more optimized new core, adding more computational power and features,
with no negative implications on the current design.
The
SHIVA processor core architecture, offers true seamless integration
with other IP cores (SoC Design), and simplifies the overall design.
Advantages
The
type of the high level programming language does not matter now.
Difference
between heterogeneous tasks is not a problem already.
Designing
with the SHIVA processor core, promotes a design recursive divide
and conquer approach, which saves time, compared to coding in RTL
a new processor, or adding new instructions to the current processor.
The
complex state machines are distributed by the ILP compiler between
the processor's cells in the core, which greatly reduces the optimization
time.
The
management of the tasks distributed inside the design, and the whole
software management is left to the ILP compiler which optimizes the
partitioning of the design.
Suitable
in designs with very high data throughput manipulation requirements,
the SHIVA processor core,
allows very high degree of flexibility of the programing code.
The functional changes can be made to the chip's operation using not
only firmware, but also the highest level of abstraction languages
/C, C++, Ada, .../
Additionally, by employing the SHIVA
processor core in SoC designs, a single chip can have extendable performance
and configurability, which can target different products in one field
of application, and simplify the SoC integration process in magnitudes.
Designing
with the SHIVA core requires knowledge of,
what you want,
how you want it,
and the way you want it.
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