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SHIVA Factsheet
The
SHIVA Reconfigurable Processor Core
Optimized configuration for the algorithm(s) to be used in the target
architecture.
The modular configurational approach allows the designer to exploit
different decisions with different trade-offs main-clock frequency,
versus, silicon area (depending on the application, market and the
effort available).
Design
types:
 -
Synchronous - available
-
Asynchronous - (suitable for mobile applications with critical power-save
requirements) - planned
for the next release.
Core options
Hardware
Description Language - VHDL
Configurable
VLIW program sequencer(s).
Configurable
number of VLIW program sequencers.
Configurable
number of address generators
/programmable on-the-fly
or configured from the program memory/.
Variable
number of data buses.
Variable
data bus width of the core.
Variable
data bus width of each of the blocks in the core.
Variable
number of program data/address buses.
Variable
program bus data width.
Self
re-configuration ability in real time.
Multi
package design split /The core can be split in to two or more packages/.
Math Units and ALU
Configurable
number of independent computational units, dividers, multipliers,
adders, subtractors, adder/subtractors, MACs, and custom defined.
Optional
available to the configuration, are floating point divider and floating
point multiplier.
Single
cycle MAC instruction execution.
Single
cycle ALU, ADD, SUB, with register read/store execution.
Single-cycle
bit arithmetic execution.
Registers
Configurable
number, and addition of memory blocks.
Confugurable
number of internal registers and memories.
All
registers and memories, are interchangeable (except the status registers).
Configurable
number of internal data temporary registers.
Program
Control
Parallel
instruction distribution and execution.
Separate
(and/or multiple) program and data buses.
Configurable
number of internal control temporary registers.
Interrupts
Configurable
interrupt unit.
Nested
interrupts support.
Cache
Memory
Configurable
internal data/program cache.
Memory
Management
Configurable
memory management unit.
Timers/Counters
The
timer/counter blocks can be tailored and integrated tightly in the
core.
The
timers/counters can be used as timers or counters depending on the
configuration. Reconfigurable on-the-fly.
I/O DMA
Timers
/ counters and the DMA blocks, offer extensive control over the I/O
data transfer.
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